Low-power architecture exploration algorithm for AMBA3.0 AXI bus

Abstract

System-on-chip communication architecture have a significant impact on the performance and power consumption of modern multi-processors system-on-chips(MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus matrix architecture synthesis at system-level. Our paper has two contributions. First, we made the bus power model of bus matrix communication architecture AMBA 3.0 AXI for fast system-level exploration. Second, we incorporated this bus power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the low-power bus matrix architecture. Experimental results show that our bus power model incur less than 1\% average error compared to gate-level models. Furthermore, our low-power architecture exploration algorithm can reduce power consumption by 66.8\% compared to a fully connected matrix, and 20.1\% compared to a maximally connected reduced matrix. The area is also reduced by 73.7\%and 20.2\%, compared to the fully connected matrix and maximally connected reduced matrix respectively.