Disparity estimation method and processor architecture for real-time image processor실시간 이미지 프로세서에 적합한 시차 추정 방법 및 프로세서 아키텍쳐

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Stereo vision is inferring 3D structure of a scene from two or more images taken from different viewpoints. In stereo vision, there are two primary problems, correspondence search and reconstruction. Correspondence search is also called stereo matching, and this is finding the corresponding pixels from two or more images. Correspondence search is an important problem, because correspondence search is computationally expensive and consumes much time among the whole processing of finding disparity map. The issues of correspondence search are how to reduce the complexity of computation and how to get disparity map which is similar to ground truth disparity map as possible. In this thesis, a new disparity estimation method is proposed and also the architecture of image processor for real-time disparity estimation is proposed. The proposed method is focusing on processing textureless regions. The proposed method uses edge values of images for classifying textureless regions. If pixel numbers that have larger edge value than edge threshold value in support window are less than 5% of window size, the support window region is classified into textureless region. If a region is textureless, window shape is changed from square window to cross window. The change of window shape gives the effect of global-like window and can check the textureless regions. The proposed processor architecture is well-designed for this proposed disparity estimation method. To reduce the latency, double buffer is used for storing next frame and internal memories are exploited to store absolute difference results of previous pixels. To improve the throughput, slice-by-slice processing is adopted too.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2008
Identifier
297179/325007  / 020063230
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2008.2, [ vii, 60 p. ]

Keywords

Disparity Estimation; Real-Time; Processor Architecture; Hardware; 시차 추정; 하드웨어 구조; 실시간; Disparity Estimation; Real-Time; Processor Architecture; Hardware; 시차 추정; 하드웨어 구조; 실시간

URI
http://hdl.handle.net/10203/38562
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=297179&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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