A 6.4Gbps on-chip eye opening monitor with 4ps, 4mV resolution for next generation high speed memory I/O = 차세대 고속 메모리의 입출력단에서의 4ps, 4mV해상도를 갖는 6.4기가bps급의 eye opening monitor 구현

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These days, high speed data communication is the main issue of the IT industry. In the near future, the data rate of differential serial links will be dramatically increased including memory product. Memory products are an important component in electrical systems, but can also bottleneck system speed performance. This is because the data transmission speeds of memory I/O is lower than for other components. Industry has tried to increase the data speed of memory I/O as with other components, so that it is clear that the data rate of memory product also will be rapidly increased. Thus, high speed data transmission is becoming more and more important in general electrical devices. In this situation, channel loss becomes a serious problem for high speed data transmission on the order of Gbps. Overcoming channel loss is an important issue in high speed data transmission research. Memory interfaces also have problems of channel loss, as with other general systems. Many companies and laboratories have studied ways to enhance the performance of data transmission. Simulation of the designed circuit is an important and unique solution for verification of the traditional design procedure. In this work we apply new technology for enhancing the performance of the system in real products. Chip designers want to know how the product works in the real world, not just simulation. On-chip measurement is difficult and uncertain. Therefore we need an on-chip eye opening monitor for verification. An eye opening monitor can provide us with information about the on-chip eye diagram. The chip designer can receive information about the on-chip eye diagram, which shows what the problem on designed circuit is and how the system works. In this research, we propose to develop an on-chip eye opening monitor with 4ps, 4mv resolution and +/- 6ps uncertainty which means effective time resolution for application to next generation memory I/O, and to use a 65nm memory process (where the effec...
Kim, Joung-Horesearcher김정호researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
268865/325007  / 020053911

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2007. 8, [ xi, 79 p. ]


Eye Opening Monitor; Next generation high spped memory I/O; 아이오프닝모니터; 차세대 고속 메모리 입출력단; Eye Opening Monitor; Next generation high spped memory I/O; 아이오프닝모니터; 차세대 고속 메모리 입출력단

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