Design and implementation of memory architecture for portable 3D rendering IP

Abstract

In this thesis, the memory architecture for portable 3D rendering IPs was designed and implemented. In order to reduce system memory bandwidth and to enhance rendering performance, it adopts a graphics cache, a separate graphics memory and an efficient RMW control scheme. Since graphics caches including depth cache, frame cache and texture cache reduce external memory access, graphics caches are used to reduce memory bandwidth and power consumption. Even with those caches, required memory bandwidth is still higher than the graphics system can provide. To reduce system memory bandwidth further, a separate graphics memory architecture is proposed. The proposed architecture uses external SRAM as a graphics memory. By using separate graphics memory, the system memory bandwidth is reduced to less than 40MBytes/sec. To reduce graphics memory latency, an efficient RMW control scheme is proposed. This scheme uses two independent clocks between the rendering core and graphics memory. By using twice higher clock rate, the memory module can perform read and write operations in one rendering clock cycle. The proposed memory architecture is used to implement a portable 3D rendering IP. Board-level implementation was performed for the verification of the proposed architecture. In the board-level implementation, the rendering IP operates at 10MHz and it shows 20Mpixles/sec. The estimated power consumption from the simulation is 29mW. By using proposed memory architecture, the 3D-performance, calculated by $\frac{pixel fill rate}{power consumption}$, is enhanced by 140 times than that with a rendering IP without the proposed memory architecture.