In these days, data transfer rate of DDR(Double Data Rate) graphic memory has been increased up to 1.4Gbps/pin. As data transfer rate increases, controlling of timing noise becomes more important. Especially the jitter of I/O clock makes it difficult to implement over Giga-bps graphic memory.
Generally, graphic memory has Delay Locked Loop(DLL) to make synchronization of data output and external clock. However, there are many repeaters on DLL replica path and I/O clock tree, because of long lossy line effect[1]. As I/O clock frequency and chip size increases, more repeaters are required. Increased number of repeaters which are very sensitive to on-chip power ground noise, causes increased amount of clock jitter. And long I/O clock distribution causes increment of delay because of on-chip wire RC delay.
In this paper, chip package hybrid I/O clock distribution scheme has been proposed and applied to DLL replica path and I/O clock tree. Chip package hybrid clock distribution means that some parts of on-chip line are routed on package layer instead of on chip lines. Interconnection resistance of package trace is about 1000 times less than that of on chip line and capacitance is about 5 times less than that of on chip line. Therefore, I/O clock path delay can be reduced dramatically because of the low interconnect RC delay on package[2],[3]. Moreover, chip package hybrid clock distribution doesn’t need repeaters so it is possible to decrease I/O clock jitter. Through the proposed chip package hybrid scheme, I/O clock for 2Gbps DDR graphic memory has been achieved.