(An) area-efficient lifting-based DWT processor for JPEG2000

Abstract

The 2D DWT processor is the key component in JPEG2000 encoding system which has increasing needs as new generation still image compression. The previous DWT architecture had large area to compute complex operations and to save large immediate values. In this thesis, an area-efficient lifting-based DWT architecture is proposed. At first, the proposed architecture reduces the computation and the memory bandwidth of DWT using lifting-based DWT algorithm. Next, the structure of buffer used in previous lifting-based DWT architecture is analyzed as middle buffer, immediate buffer and repeat buffer. The middle buffer is replaced by pipeline registers and the repeat buffer is reduced from size of $N^2/4$ to 2N using the proposed recursive architecture and band-processing. Although the size of immediate buffer is increased from 2N to 6N, the total size of buffer is reduced from $N^2/4+5N$ to 8N. Therefore the required size of memory is reduced to 88.57% and 94.03% in the case of 256×256 image and 512×512 image respectively. The proposed architecture is implemented in Verilog HDL and synthesized in Hynix 0.25um technology. The operating frequency and logic area without memory are 250MHz and 43765 gates respectively. The required size of memory is 4kB for 256x256 image.