Design and implementation of low-power embedded 3D graphics rendering engine for mobile applications using the embedded memory logic technologyEmbedded memory logic technology를 이용한 휴대용 기기를 위한 저전력 embedded 3D graphics rendering engine의 설계및 구현

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Low-Power Embedded 3D Graphics Rendering Engine (E3GRE) for mobile applications is designed and implemented using 0.18㎛ Embedded Memory Logic technology as a part of the RamP-II PDA chip. The E3GRE can draw 2.22Mpolygon/sec at 20MHz, which means 71Mpixel/sec fill rate, by utilizing the wide-bus of the embedded Frame-Buffer based on the Virtually Spanning 2D Array (ViSTA) architecture. The memory interface circuit, which is optimized for Read-Modify-Write data transaction, dynamically reconfigures 640bit Pixel Processor bus to 2048bit memory bus at every cycle controlling 12 x 512Kb SDRAM-compatible macros independently. These DRAM macros compose 6Mb Frame-Buffer with Selective and Alternative Line-Block Activation (SALBA) memory mapping which shows 3.2Gbyte/sec memory bandwidth at 20MHz. Partial Wordline Activation (PWA), Selective Macro Activation (SMA), and Partial I/O Activation (PIA) reduce the power consumption of the embedded DRAM macros. With the help of ViSTA architecture and SALBA memory mapping, the clock speed of E3GRE core can be lowered to reduce its power consumption. It runs at a quarter frequency of the system clock, i.e. at 20MHz. The embedded frame-buffer is synchronously accessed with 100MHz clock and internal clock circuit generates and synchronizes all clocks with the DLL and the clock multiplier. The E3GRE features Gouraud shading, alpha-blending for transparency, 16bit depth-comparison, double-buffering for flicker-free animation, and video transfer. The internal Serial Access Memory (SAM), which consists of 1.5Kb SRAM, directly transfers 24bit true-color RGB video data to display device such as an LCD covering 256 x 256 screen size. The E3GRE, which has 190,231 logic transistors, 6Mb DRAM and 1.5Kb SRAM, is designed with full-custom method to minimize its power and area using 0.18㎛ Hyundai CMOS EML process with 3-poly 6-metal layers. A 1.5V power supply is used in the logic core and 2.5V is used in the memory. The E3GRE shows 122mW power...
Advisors
Yoo, Hoi-Junresearcher유회준researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2001
Identifier
165871/325007 / 000993329
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2001.2, [ [vii], 102 p. ]

Keywords

Low Power; Chip; Circuit Design; 3D Graphics; Mobile; 휴대용; 저전력; 칩; 회로설계; 3차원 그래픽

URI
http://hdl.handle.net/10203/37444
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=165871&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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