$.8 \um m$ CMOS를 이용한 1.485 Gb/s 병렬화기의 설계1.485 Gb/s deserializer chip design using $.8 \um m$ CMOS for HDTV application
- Advisors
- 조규형researcher; Cho, Gyu-Hyeongresearcher
- Description
- 한국과학기술원 : 전기및전자공학과,
- Publisher
- 한국과학기술원
- Issue Date
- 1999
- Identifier
- 150851/325007 / 000973233
- Language
- kor
- Description
학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1999.2, [ vi, 78 p. ]
- Keywords
디멀티플렉서; 쿼더리코릴레이터; 피엘엘; 병렬화기; 고해상도 티브이; 루프이득조절; Loop gain control; Demultiplexer; Quadricorrelator; PLL; Deserializer; HDTV
- Appears in Collection
- EE-Theses_Master(석사논문)
- Files in This Item
- There are no files associated with this item.
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