#### (A) 10-bit 300 MSample/s pipelined ADC using time-interleaved successive approximation register ADC = 시간병렬 연속근사 데이터변환기를 이용한 300 MSample/s 10-bit 파이프라인 아날로그-디지털 데이터변환기

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As the multimedia and communication business are grown, the demand of ADC with high speed and low power consumption is skyrocketed. As a CMOS process is advanced, however, the analog/Mixed signal circuit design is getting harder. Thus, the architectural innovation is needed to the meet the demands. A pipelined ADC architecture is suited to the medium to high resolution and sampling speed due to their high throughput. However, since the architecture requires Opamps having high DC gain and bandwidth, the pipelined ADC consumes lots of power, and their energy efficiency get worse as the operation speed go into hundreds mega-hertz. In order to overcome the limitation of the pipelined ADC, A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power hungry sample-and-hold amplifier can be removed and rail-to-rail input can be used. In addition, feedback factor $\beta$ of the first inter-stage amplifier can be increased, which significantly reduces the power consumption of the first opamp. Simulation results in 90 nm CMOS show that 8.8 bits of effective-number-of-bits (ENOB) at 300 MHz sampling rate can be achieved while consuming 77mW at 1.2V supply. Figure-of-merit of the proposed ADC is 554 fJ/Conv. However, measurement results show that 7.1 bits of ENOB at 250 MHz sampling rate is achieved while consuming 80 mW at 1.2 V for digital and 1.3 V supply for analog part, although the measurement is on-going. The alteration of the domain for the signal processing also can be considered in order to overcome the limitation of analog/Mixed signal circuits. As CMOS process scaling has moved into the nanometer regime, time-domain resolution that benefits from excellent switching speed of the scaled MOS device is superior to voltage-domain resolution. A time-based SAR ADC using a pulse wi...
Cho, Seong-Hwanresearcher조성환researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419169/325007  / 020083111
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ (A) 10-bit 300 MSample/s pipelined ADC using time-interleaved successive approximation register ADC], [ x, 85 p. ]

Keywords

ADC; analog-digital converter; data converter; Successive Approximation Register; pipeline ADC; 파이프라인 아날로그 디지털 데이터변환기; 파이프라인 데이터변환기; 아날로그-디지털 데이터 변환기; 데이터변환기; 연속근사 데이터변환기

URI
http://hdl.handle.net/10203/36597