(A) fast simulation methodology in VLSI circuits = VLSI 회로에서의 고속 시뮬레이션 방법론에 관한 연구

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dc.contributor.advisorPark, Kyu-Ho-
dc.contributor.advisor박규호-
dc.contributor.authorPark, Kwang-Il-
dc.contributor.author박광일-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued1999-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=151015&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36514-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1999.2, [ xi, 132 p. ]-
dc.description.abstractIn designing VLSI circuits, the simulation of the circuits is an inevitable step to verify the behavior and timing of the circuits. As the complexity and size of VLSI circuits increase, the performance of simulation becomes more and more important. The event-driven simulation that is often used in designing VLSI circuits depends on the number of events that occur during the simulation. In this dissertation, a methodology to reduce the number of events is proposed and implemented for both sequential and combinational circuits. The methodology is based upon the classification of events into two categories, such as sensitive events and insensitive events, according to the necessity of simulation. The elimination of the insensitive events may reduce the number of events, which results in the acceleration of the simulation. The optimization algorithms that identify the eliminative events for both sequential and combinational circuits are developed. Our algorithm is applied to several real programs such as DP32 and DLX. The results show that automatically optimized VHDL programs run almost two times faster than original ones. In the optimization algorithm for combinational circuits, Boolean difference is used to find the eliminative events. Most time of optimization is taken in calculating Boolean difference (sensitivity function). Furthermore, the size of combinational circuits, that is, the number of variables, greatly effects the performance of the algorithm. To overcome this drawback, a new algorithm that calculates Boolean difference faster than an existing method is also proposed in this dissertation. The new algorithm is based upon a newly found property of Boolean difference. The property is the distributivity of Boolean difference over cofactor expansion. Another approach to speed up simulation is to distribute simulation workload among processors of a parallel computer. The simulator of Time Warp, a popular method of parallel simulation, is implemented. I...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectVHDL-
dc.subjectSimulation-
dc.subjectEvent suppression-
dc.subject사건 감소-
dc.subjectVHDL-
dc.subject시뮬레이션-
dc.title(A) fast simulation methodology in VLSI circuits = VLSI 회로에서의 고속 시뮬레이션 방법론에 관한 연구-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN151015/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000955128-
dc.contributor.localauthorPark, Kyu-Ho-
dc.contributor.localauthor박규호-
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EE-Theses_Ph.D.(박사논문)
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