Development of flash memory using high-k dielectrics by the improvement of charge trap layer and blocking oxide layer and its theory = 고유전막을 이용한 전하포획막과 차단산화막의 향상을 이용한 플래쉬 메모리 개발 및 그 이론

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In this dissertation, advanced charge trap type flash memory has been developed through blocking oxide layer and charge trap layer engineering by rare earth high-K oxides. Rare earth oxide was selected due to its high dielectric constant and relative high bandgap and band offset. To enhance flash memory property by blocking oxide engineering, GdAlO was applied to blocking oxide layer. It was found that non-volatile memory properties are strongly dependent on structural and compositional change of blocking oxide. Leakage current decreased with Gd concentration due to the increase of physical thickness. However, above 50% Gd concentration, GdAlO thin film tends to be crystallized after source/drain activation temperature. After crystallization, leakage current increased, therefore erase window reduced. In retention property, charge loss increased with Gd concentration due to its lower band offset. However, above 50% Gd concentration, GdAlO thin film was crystallized, and bandgap and band offset increased with Gd concentration. Therefore, charge loss decreased with Gd concentration after crystallization. Although leakage current increased after crystallization, the bandgap and band offset of blocking oxide increased, and retention property was enhanced. To improve retention property, charge trap layer has been improved by dopant. Very thin rare earth oxide layer was introduced into silicon nitride without changing a total gate stack EOT value. Among various dopants, Lanthanum oxide dopant showed similar program/erase speed, but retention property was improved. There is an optimum condition of La concentration and the position of dopant in silicon nitride. To maximize the effect of doping and to control the doping effect easily, ALD process of silicon nitride has been developed at low deposition temperature. To enhance thin film property and ALD process, hydrogen plasma treatment was introduced. Therefore, high growth rate and high throughput was achieved at low te...
Advisors
Cho, Byung-Jinresearcher조병진researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
466443/325007  / 020037259
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2011.2, [ xii, 112 p. ]

Keywords

blocking oxide; high-K dielectric; flash memory; SONOS; charge trap layer; 희토류 산화물; 전하포획막; 차단산화막; 고유전체; 플래쉬 메모리

URI
http://hdl.handle.net/10203/35630
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=466443&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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