Design of a 2.4-GHz low-power single-chip CMOS receiver front-end and frequency source for wireless sensor network무선 센서망을 위한 2.4-GHz 저전력 단일 칩 수신기 전단 및 주파수 생성기의 설계

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dc.contributor.advisorHong, Song-Cheol-
dc.contributor.advisor홍성철-
dc.contributor.authorSong, Taek-Sang-
dc.contributor.author송택상-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2006-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=258153&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35384-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.2, [ xii, 137 p. ]-
dc.description.abstractDue to rapidly growing markets of battery-operated wireless sensor network (WSN), the needs for extremely low-power single-chip wireless transceivers have drawn wide attention. Especially, power reduction of receiver is a key issue to improve power efficiency of transceiver. This is because sensor nodes spend far more time in receiving (waiting for wake-up signal) than in transmitting (answering the requests). Therefore the receiver power consumption is the most critical issue in the design of low-power transceivers, even though the power level required in transmit mode is an order of magnitude higher. Thus, the methods focused on power reduction without sacrifice of performance should be devised to increase life-time of sensor nodes. This thesis proposes and implements receiver front-end and frequency source, which are the most power-consuming blocks and determine the entire receiver performance. Because sensor nodes are sensing and transmitting slowly varied data of environmental and biological information, new network specifications suitable for low-power and low data rate have been generated. Transmitted signal at 2.4-GHz, which is modulated by FSK, has an output power of 10 dBm to link sensor nodes. And a bit-error rate (BER) of $10^{-3}$ and sensitivity of -90 dBm is required in receiver. As a result, receiver performance should satisfy a noise figure of 20 dB with an IIP3 of -33.5 dBm and phase noise of -93 dBc/Hz. To satisfy the receiver specifications with very low-power consumption, we propose and demonstrate two important blocks in receiver, which are the largest power consuming components. First, a 2.4-GHz fully integrated CMOS frequency source using a current-reused differential frequency multiplier and a 1.2-GHz VCO are proposed in order to reduce power consumption of receiver. The proposed frequency multiplier can generate differential output signals with differential input signals and reduce power consumption by reusing DC bias current. In...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectfrequency multiplier-
dc.subjectfrequency source-
dc.subjectreceiver front-end-
dc.subjectwireless sensor network-
dc.subjectcurrent-reusing-
dc.subject전류 재사용-
dc.subject주파수 체배기-
dc.subject주파수 생성기-
dc.subject수신기 전단-
dc.subject무선 센서망-
dc.titleDesign of a 2.4-GHz low-power single-chip CMOS receiver front-end and frequency source for wireless sensor network-
dc.title.alternative무선 센서망을 위한 2.4-GHz 저전력 단일 칩 수신기 전단 및 주파수 생성기의 설계-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN258153/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020025155-
dc.contributor.localauthorHong, Song-Cheol-
dc.contributor.localauthor홍성철-
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EE-Theses_Ph.D.(박사논문)
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