Pixel-Level characterization and optimization of CMOS image sensor in low-voltage operation저전압 CMOS 이미지 센서에 대한 픽셀 레벨의 특성화 및 최적화

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The significant increase of market demands for low-cost and high-performance CMOS image sensor makes the development of CMOS image sensor more aggressive. However, lots of bottlenecks start to be found at optics and electronic systems recently. Most of all, recent degraded pixel performance in low voltage operation is one of the most intricate problems. Especially, as sub-0.18um CMOS process is adopted, the supply voltage is reduced less than 2.5V, which inevitably opens the possibility of incomplete reset of PPD, because the photodiode reset voltage, i.e., the pinning voltage $(V_{pin})$ can not be accordingly reduced. Furthermore, the potential barrier which exists between photodiode and charge transfer (TX) transistor due to surface implantation on top of the pinned photodiode (PPD) should be designed to be suppressed during reset and charge transfer operation. However, it is not easily obtained anymore due to the reduced operational voltage margin between the $V_{pin}$ and the floating diffusion (FD) voltage. Under these circumstances, prior to the introduction of non fully-depleted pinned photodiode (NFD-PPD), we first propose DC and noise setup as a cost-effective inspection tool in which a pixel-level characterization can be conducted using an external ADC board (Gage 1610 model). Using photodiode programming in the developed DC and noise setup, various performance parameters are extracted from a single pixel test pattern including dark current, $V_{pin}$, well capacity, the FD capacitance (conversion gain), the ratio of the PD capacitance over the FD capacitance, dynamic range, charge transfer curve, photon transfer curve and so on. The input-referred noise levels due to the used external ADC board and overall measurement setup are also experimentally measured, which verifies that the measured noise level, for example in PTC curves, is sufficiently lowered and not affected in the measurements. The measured minimum input-referred noise voltage power l...
Advisors
Hong, Song-Cheolresearcher홍성철researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2006
Identifier
258152/325007  / 020025110
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.8, [ xiii, 167 p. ]

Keywords

device scaling; pinning voltage; pinned photodiode (PPD); four-transistor structure; CMOS image sensor; non full-depleted pinned photodiode (NFD-PPD); 전압 스케일링; 소자 스케일링; 피닝 전압; 핀드 포토다이오드; 4-트랜지스터 구조; 씨모스 이미지 센서

URI
http://hdl.handle.net/10203/35383
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=258152&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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