This thesis presents new technology that accelerates the system verification. The proposed method partitions testbench program into software and hardware such that the execution of the hardware-mapped testbench is accelerated, thus enabling fast functional simulation. Traditional functional verification methods, which are based on logic simulation, become very time consuming as design complexity increases. To speed up functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between software simulator and hardware accelerator is becoming a new critical bottleneck. To reduce the communication overhead, it is suggested to identify a part of the testbench tightly coupled with the hardware-mapped DUT and move it into the hardware accelerator by converting testbench synthesizable. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to the conventional hardware accelerated simulation while maintaining the cycle accuracy and strict compatibility with the original testbench.