Communication-efficient hardware acceleration for fast functional simulation = 고속 시뮬레이션을 위한 효율적인 하드웨어 가속 방법

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This thesis presents new technology that accelerates the system verification. The proposed method partitions testbench program into software and hardware such that the execution of the hardware-mapped testbench is accelerated, thus enabling fast functional simulation. Traditional functional verification methods, which are based on logic simulation, become very time consuming as design complexity increases. To speed up functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between software simulator and hardware accelerator is becoming a new critical bottleneck. To reduce the communication overhead, it is suggested to identify a part of the testbench tightly coupled with the hardware-mapped DUT and move it into the hardware accelerator by converting testbench synthesizable. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to the conventional hardware accelerated simulation while maintaining the cycle accuracy and strict compatibility with the original testbench.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2005
Identifier
244884/325007  / 020005059
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.2, [ x, 108 p. ]

Keywords

Simulation acceleration verification; communication-efficient hardware; 효율적인 하드웨어 가속 방법; 시뮬레이션 가속 검증

URI
http://hdl.handle.net/10203/35265
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=244884&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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