Design of a 2.4 GHz low power and highly linear single-chip CMOS receiver2.4GHz 저전력 고선형 단일칩 CMOS 수신기의 설계

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This work presents a 2.4 GHz single-chip low power receiver realized in a 0.18 mm CMOS process. Among the various receiver architectures, direct conversion receiver (DCR) is a viable candidate solution for low cost and low power. However, there are several problems in using DCR such as large DC offset, LO leakage. 1/f noise and I/Q mismatch. To alleviate these problems, single IF DCR architecture has been proposed which combines the advantage of both the super-heterodyne and DCR architectures. The linearity performance requirement becomes more critical in modern RF communication system. Especially, for the use at unlicensed 2.4 GHz ISM bands, highly linear receiver is required for the immunity to the various interferer signals of different standards. The linearity of the LNA and mixer directly related to that of the receiver front-end. Usually, the nonlinearity of the receiver front-end is limited by that of the down-conversion mixer and thus a highly linear mixer is required. Since IIP3 is approximately proportional to the DC power consumption, it is a great challenge to achieve high linearity at low power. In this paper, a highly linear low power 2.4 GHz CMOS receiver based on current amplification and mixing using current mirroring technique is proposed. This is based on single IF DCR and thus suitable for silicon integration. A receiver front-end circuit operating at 2.4 GHz is designed and fabricated in 0.18㎛ CMOS process. The circuit technique to improve the linearity of the receiver is explained in detail and the fabrication results are reported. In the proposed mixer, linearity is greatly improved by using current mirror amplifier and transconductance linearization using multiple gated transistors. Also, a low power CMOS receiver baseband analog chain based on alternating filter and gain stage is reported. The optimization method has been proposed with the derivation of the relations between dynamic range and current consumption of the analog filter-a...
Advisors
Lee, Kwy-Roresearcher이귀로researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2004
Identifier
240733/325007  / 020005020
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.8, [ v, 137 p. ]

Keywords

CMOS; FREQUENCY MULTIPLIER; LOW POWERQUENCY DOUBLER; LINEARIZATION; SINGLE IF; CURRENT AMPLIFIER; CMOS RECEIVER; PINCH-OFF CLIPPINGERSONALIZED SERVICE; 개인화 서비스; 핀치 오프 클리퍼비쿼터스 컴퓨팅; CMOS; 주파수 체배기; 저전력포머; 선형화; CMOS 수신기; 전류 증폭기; 단일 IF

URI
http://hdl.handle.net/10203/35255
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=240733&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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