All-digital fast-locking clock synchronization methods using synchronous mirror delay

Abstract

Phase-locked loop (PLL) and delay-locked loop (DLL) are widely used in solving the problem of the clock synchronization. However, several hundreds of clock cycles are required for both PLL and DLL to lock the system. Furthermore, PLL and DLL are sensitive to the process, voltage, and temperature (PVT) variations. On the other hand, a synchronous mirror delay (SMD) requires only two clock cycles in order to suppress the clock skew. Besides, the SMD is robust to the PVT variations because it consists of only digital circuits. This dissertation proposes two techniques of the clock synchronization using the SMD. First, an area-reduced interleaved synchronous mirror delay (ARI-SMD) is proposed in order to reduce both the circuit area and the consumption power. The conventional interleaved SMD has a pair of forward delay array (FDA) and backward delay array (BDA) in order to reduce the clock skew of the conventional SMD by half. However, the proposed ARI-SMD requires only one FDA and one BDA by using two multiplexers. Simulation results show that the proposed ARI-SMD has an advantage of about 40% area reduction and about 20% consumption power reduction compared to the conventional interleaved SMD. And, the total locking time of the ARI-SMD is 4 clock cycles. Second, a high-resolution SMD is proposed in order to reduce the clock skew even further. It is an extended concept of the ARI-SMD. While ARI-SMD increases its resolution by two, the high-resolution SMD increases its resolution by eight. The high-resolution SMD reduces the clock skew in two steps. Coarse phase lock is achieved by the conventional SMD. Fine phase lock is achieved by the successive approximation register for the sake of fast locking. Measured results show that the maximum clock skew of the proposed high-resolution SMD is 140psec in the frequency range from 170MHz to 230MHz and that the consumption power is 14.85mW at 230MHz in a 0.35㎛ 1-poly 4-metal CMOS technology. The RMS jitter and the Peak-to-P...