Cache line overlapping

Abstract

Cache memories in contemporary processors play an important role to reduce a speed gap between processor and main memory. For this reason, reducing cache misses is becoming increasingly significant since it has a dramatic effect on overall performance of computing systems. It is observed that over 50% of bytes in a data cache are zero-valued by studying the behavior of general benchmark programs. Due to this characteristic, the majority of word (4 bytes) values in this cache can be represented in a half word or less. For reducing this waste of zero-valued spaces in the cache, we propose a novel cache architecture, Overlapped Cache (OVLPC), which allows one cache line entry to hold up to two cache lines. Our experiments with respect to SPEC2000 benchmark programs show that by extending a baseline direct-mapped cache with the scheme overlapping cache lines we can obtain reductions in miss rate ranging 1%~65% against a baseline direct-mapped cache. It is also demonstrated that by augmenting conventional set-associative caches with our scheme considerable reductions in miss rate are acquired. Notwithstanding, our scheme has reasonable overheads such as delay and storage and is more practical to be implemented on a real hardware than previously-proposed related designs.