New hardware-based clock synchronisation for the Byzantine fault

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dc.contributor.authorBaek, Yunju-
dc.contributor.authorLee, Heung-Kyu-
dc.contributor.authorYoon, Hyunsoo-
dc.date.accessioned2008-03-11T03:19:05Z-
dc.date.available2008-03-11T03:19:05Z-
dc.date.issued1992-10-
dc.identifier.citationElectronics Letters, Vol. 28, No. 21, P.2018 - 2019en
dc.identifier.issn0013-5194-
dc.identifier.urihttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=170897-
dc.identifier.urihttp://hdl.handle.net/10203/3375-
dc.description.abstractA new approach for fault-tolerant clock synchronisation which uses digital clocks instead of the conventional PLLs(phase-locked loops) is presented. In this circuit the delay time of the clock system is much reduced and the exact maximum clock skew is obtained to guarantee the tightness of the synchronisation.en
dc.language.isoen_USen
dc.publisherInstitution of Engineering and Technologyen
dc.subjectComputer metatheoryen
dc.subjectHardware fault-tolerant clock synchronisationen
dc.subjectByzantine faulten
dc.subjectInteractive convergence algorithmen
dc.titleNew hardware-based clock synchronisation for the Byzantine faulten
dc.typeArticleen
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