Refining data layouts in code generation

Abstract

Many modern computer architectures are equipped with hardware components to reduce various costs such as code size and energy and improve the performance of the system such as execution time and memory usage. Conventional code generation techniques, however, often generates inefficient code, failing to fully utilize those hardware components and leaving much room for optimizations. In my thesis, I propose code generation techniques to better exploit strong features of three modern architectures by refining the layouts of data in storage such as memory and register file. First, I address the offset assignment problem in code generation for digital signal processor (DSP). I aim to minimize the code size and improve the performance by reducing the number of instructions solely for calculating addresses of variables. By tightly combining the offset assignment problem with code scheduling, I improve existing solutions. I also propose the reassignment of registers to minimize the costs of transferring data between the register file and the memory for the architectures equipped with register stacks. Register stack provides a virtually infinite-sized register file to processor through overflowing the register values to the memory whenever the total height of the register stack reach a certain threshold and also filling the registers back whenever they are needed, without processor intervention. To mitigate these costs of overflowing/underflowing registers, I attempt to minimize the register stack height by reassigning register names in the code emission phase, the last phase of code generation. Finally, I propose a technique for variable assignment to mitigate the delay of memory access which is known as one of the major bottlenecks in embedded systems`` performance. I study DRAM memory layout for storing the non-array variables in code to achieve a maximum utilization of page and/or burst modes to increase memory bandwidth. I formulate relevant...