High-performance and reliable architecture synthesis problems in system-on-chip design

Abstract

In this thesis, we address four architecture synthesis and optimization problems that are highly important in system-on-chip (SoC) design: (1) an optimal architecture synthesis of arithmetic circuit using carry-save-adders, (2) layout-aware architecutre synthesis of arithmetic circuits, (3) layout-driven resource sharing in data path synthesis, and (4) code placement with selective cache activity minimization for embedded real-time system design.