Development of dual-mechanism memory device using charge trapping and ferroelectric switching for high-performance 3-D NAND flash

Abstract

This dissertation focuses on the development of dual-mechanism memory device that combines ferroelectric polarization switching as an additional memory engine, rather than using only the existing charge trapping mechanism to drastically improve the memory characteristics of 3D NAND Flash. The first purpose of this study is to propose an idea for applying the dual-mechanism to single gate stack and to confirm its feasibility. The second purpose of this study is to verify whether the dual mechanism effect is actually worked based on the performances of the proposed memory device. Finally, the third purpose of this study is to present a method to maximize the synergistic effect and examine the practical applicability through the memory performance of the optimized gate stack. As the number of bits of a cell increases, the allowable Vth window of each state becomes very narrower, and the program/erase time takes longer. Likewise, a more strict retention characteristic is also required as the allowed Vth window becomes narrower. The endurance characteristics are also degraded as the number of Incremental Step Pulse Programming (ISPP) pulses increases. The most effective way to overcome this problem is to increase the maximum memory window. As an idea for this, we propose to apply an additional memory mechanism, ferroelectric polarization switching, to the gate stack. As a result of fabricated proof-of-concept memory device, a memory window improved by up to 96% was achieved compared to reference charge trap memory having the almost identical equivalent oxide thickness (EOT). In addition, it was confirmed that the dual-mechanism memory exhibits improved retention characteristics than the charge trap memory for cells with the same memory window. This approach can pave the way to further increases of bits/cell toward PLC and beyond in 3D NAND Flash memory.