Improvement of data reduction performance for space-borne sar using digital filter bank and polyphase filter

Abstract

In designing a space-borne SAR system, data reduction is an important technique since the downlink capability of the data-link to the ground station is significantly insufficient compared to the data volume generated from the SAR system. For the SAR data reduction, dechirp-on-receive (DoR) method has been widely used in many SAR systems. This method requires to have deramping hardware in the SAR system and extra control for deramping operation that lead to increase the complexity of the system. This dissertation presents two SAR data reduction methods based on on-board digital signal processing. This research presents the data reduction performance of the two methods, and also demonstrates they can be implemented on space-grade FPGAs. The first method is a digital filter bank-based method that does not require deramping hardware in the SAR system. It shows superior SAR data reduction performance compared to the DoR method. In this dissertation, the concept and the structure of this method are presented, and the quantitative analysis of SAR data reduction performance and the comparison with the DoR method are presented. In addition, this research proves that this method can be used for space-borne SAR systems by presenting the implementation based on space-grade FPGAs. The second method can be used when it is required to develop a digital equipment that shall be linked to the existing SAR RF equipment containing deramping hardware already. This method is based on polyphase filter technology and shows better SAR data reduction performance than DoR method. This research utilizes non-integer ratio decimation for the additional data reduction. In this dissertation, an efficient FPGA resource sharing computation block is proposed, and also a set of combinations of polyphase filters are studied for the efficient filter structure to implement non-integer decimation with various decimation ratios. In addition, it is shown that this method is applicable to space-borne SAR systems by presenting FPGA resource usage analysis and timing margin analysis targeting space-grade FPGAs.