Development of vertical channel thin-film transistor array for the ultra-high resolution display

Abstract

Recently, the display industry is undergoing a lot of changes. Not only the needs for the Ultra-high resolution over 8K, which is a market-leading technology, but also the new technologies represented by virtual reality (VR) and augmented reality (AR) are getting much attention as the killer applications for the next-generation display. However, there remain several critical issues to realize these new technologies, and one of them is a pixel density of the display. The latest displays for mobile devices on the market usually have about 600 pixels per inch (PPI), and even a high-end 8K display for VR/AR does not exceed 1000 PPI. Their specifications are not enough to provide a sense of reality to the VR or AR users, due to the screen-door effect. To solve this problem, higher pixel density up to several thousands of PPI is strongly required for the next-generation display. From that point, the concept of vertical channel structure thin-film transistor (VTFT) have been suggested as a promising solution. VTFT occupies less area than the back-channel etch (BCE) structure thin-film transistor (TFT), which is known to have the smallest footprint among the conventional TFT structures, due to the vertical channel structure. Therefore, it is able to reduce the size of each pixel and offer improved pixel density of display. In addition, it is possible to fabricate the sub-micron scale channel length TFT by utilizing the pre-existing photolithography equipment for display industry, which means that the enhancement of current drivability, and on-current level can be achieved with lower manufacturing costs. In this thesis, a study on proper optimization for material, process, and device structure were conducted to fabricate the ultra-high resolution VTFT array.