Fabrication and process simulation of SOI MOSFETs with a 30-nm gate length

Abstract

We have obtained systematic simulation and experimental results for 30-nm-gate-length metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator (SOI) substrates. The two-dimensional process simulation and the device simulation were carried out to optimize the fabrication process conditions and the device characteristics of 30-nm-gate-length SOI MOSFETs. A new simple source/drain formation technique using the solid-phase diffusion (SPD) method was developed, Based on the simulation results and the SPD ultra-shallow junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors and superior device scalability.