Memory controller, semiconductor memory system and operating method thereof

Abstract

An operation method of a memory controller may include performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity, wherein the message and the internal parity are included in the internal region in a matrix form; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region