SAR-assisted continuous-time delta sigma modulator

Abstract

For power efficiency and reduced design complexity, a SAR-assisted continuous-time delta sigma modulator (CT DSM) has been proposed and researched. Using SAR ADC as a multi-bit quantizer in the modulator, the design of multi-bit quantizer is quite simple and compact. Its power consumption also could be saved. A CT DSM with delta conversion based SAR ADC has been proposed to reduce the burden of internal conversion speed for SAR ADC. The delta conversion scheme utilizing oversampling characteristic could effectively reduce the number of conversion cycle. It operates 600 MS/s with a 10 MHz BW, which has 5-bit SAR ADC as a multi-bit quantizer. The prototype was implemented in a 28 nm CMOS process and achieves a peak 67.4 dB SNDR and the power consumption of 8.9 mW A CT DSM with SAR-assisted digital-domain noise coupling (DNC) introduces a high-order continuous time (CT) delta sigma modulator (DSM) that applies digital-domain noise coupling (DNC) based on the structural advantages of the SAR ADC, which makes the implementation of second-order noise coupling very simple. Due to digital-domain implementation as well as the SAR ADC where the key building blocks are embedded for the proposed DNC, a compact and power-efficient modulator could be designed. For low circuit noise, a feedback DAC is implemented with a tri-level current steering DAC. Tri-level data-weight averaging (TDWA) improves the linearity of the DAC. With the proposed DNC and TDWA, the prototype CT DSM fabricated in a 28 nm CMOS achieves a peak 74.4 dB SNDR and an 80.8 dB dynamic range (DR) for a 10 MHz BW with an OSR of 16, resulting in a Schreier FoMDR of 174.5 dB. The chip area occupies 0.1 mm2 and the power consumption is 4.2 mW.