Stateful logic provides an attractive device-level solution in achieving in-memory computation, which can solve the critical problem of the von Neumann bottleneck - "memory wall" - in the current computer architecture. Recently, fully functional stateful logic operations and cascading are reported using a TiOx-based dual-bit memristor. In that work, all the 16 Boolean logic functions are accomplished in a stateful dual-bit memristor, which can be expanded to more complicated computational tasks. This logic scheme is much more compact compared with the current complementary semiconductor field effect transistors based logic, providing the system with great area efficiency as well as energy-saving performance. In such stateful logic device, the logic flow (cascading) is made along the time dimension. Therefore, "time efficiency" is the critical factor for estimating its performance. In this paper, two methods, changing the logic coding scheme and configuring the parallel-circuit morphology, are suggested to improve the time efficiency of the previous dual-bit memristor-based logic. By implementing the two methods, a full adder can be demonstrated with three dual-bit memristors and 12 operation steps, which corresponds to a 55.6% improvement compared with the previous work.