Writing 10 Gb/s Data Bits With Addressing Using External Cavity-Based SMFP-LDs

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Memory accessing is one of the challenging issues for utilizing the improvements in processor speed. Due to the rapid enhancement on processor speed compared to the memory accessing technique, the gap between the memory accessing and processor speed is rapidly widening. Hence, a new technique to address this issue needs to he devised. In this paper, we experimentally demonstrate the complete scheme of wavelength division multiplexing enabled memory WRITE operation in the desired memory location using single mode Fabry-Perot laser diodes (SMFP-LDs). For a proof of concept, we demonstrate writing a stream of data bits at 10 Gb/s data rate in a memory unit that consists of four single bit set-reset (SR) latches with a unique addres.s. The input data bits are stored in the respective latch of the memory bank in accordance with the address hit set along with a wurE instruction. A higher order of memory units with address decoding can be realized by increasing the higher order of decoder and the memory units. The observed optical domain waveforms at the respective nodes of each block, eye diagram, SNR, and bit error rate (BER) prove the verification of writing input data to the desired memory locations using SMFP-LDs. We observed an extinction ratio of more than 12 dB, no noise floor at the BER of 10(-)(12), and a maximum power penalty of about 2.5 dB in the proposed scheme.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-11
Language
English
Article Type
Article
Citation

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, v.25, no.6

ISSN
1077-260X
DOI
10.1109/JSTQE.2019.2911854
URI
http://hdl.handle.net/10203/262723
Appears in Collection
EE-Journal Papers(저널논문)
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