High speed JPEG coder based on modularized and pipelined architecture with distributed control

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The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.251 mu m CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported.
Publisher
SPRINGER-VERLAG BERLIN
Issue Date
2005
Language
English
Article Type
Article; Proceedings Paper
Citation

ADVANCES IN MULTIMEDIA INFORMATION PROCESSING - PCM 2005, PT 1 Book Series: LECTURE NOTES IN COMPUTER SCIENCE, v.3767, pp.466 - 476

ISSN
0302-9743
URI
http://hdl.handle.net/10203/255891
Appears in Collection
GT-Journal Papers(저널논문)
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