Self-timed interconnect with layered interface based on distributed and modularized control for multimedia SoCs

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In this paper, a high performance asynchronous on-chip bus designed in a Globally Asynchronous Locally Synchronous (GALS) style is proposed. The asynchronous on-chip bus is capable of handling multiple outstanding transactions and in-order completion to achieve a high performance, which is implemented with distributed and modularized control unit in a layered interface. The architecture of asynchronous on-chip bus is discussed and implemented for simulations. Simulation results show that throughput of the proposed asynchronous on-chip bus with multiple outstanding transactions and in-order transaction completion is increased by 31.3%, while power consumption overhead is only 6.76%, as compared to an asynchronous on-chip bus with a single outstanding transaction.
Publisher
SPRINGER-VERLAG BERLIN
Issue Date
2005
Language
English
Article Type
Article; Proceedings Paper
Citation

ADVANCES IN MULTIMEDIA INFORMATION PROCESSING - PCM 2005, PT 1 Book Series: LECTURE NOTES IN COMPUTER SCIENCE, v.3767, pp.500 - 511

ISSN
0302-9743
URI
http://hdl.handle.net/10203/255890
Appears in Collection
GT-Journal Papers(저널논문)
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