Design of an asynchronous switch based on butterfly fat-tree for network-on-chip applications

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The future System-on-Chip (SoC) design will integrate a variety of intellectual properties (IPs). The clocked bus architectures to interconnect the IPs under the deep submicron technology suffer from problems related with the clock distribution, the synchronization of all IPs, the long arbitration delay and the limited bandwidth. These problems can be resolved by adopting new interconnection architecture such as Network-on-Chip (NoC) or the asynchronous design method. In this paper, a design methodology for an asynchronous switch based on butterfly fat-tree topology is proposed. The wormhole switching technique is adopted to reduce the latency and the buffer size. The source-based routing mechanism and the output buffering strategy are used to reduce the switch design cost and increase the performance.
Publisher
SPRINGER-VERLAG BERLIN
Issue Date
2005
Language
English
Article Type
Article; Proceedings Paper
Citation

ADVANCES IN MULTIMEDIA INFORMATION PROCESSING - PCM 2005, PT 2 Book Series: LECTURE NOTES IN COMPUTER SCIENCE, v.3768, pp.538 - 549

ISSN
0302-9743
URI
http://hdl.handle.net/10203/255889
Appears in Collection
GT-Journal Papers(저널논문)
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