Scratching of Patterned Cu/Dielectric Surface Layers by Pad Asperities in CMP

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In chemical-mechanical polishing (CMP), as the rough polymer pad slides over patterned structures of metal interconnects and dielectrics the pad asperities themselves, though soft, may scratch the relatively hard layers. The fully plastically deformed pad asperities with high interfacial friction are the primary sources of pad scratching. In this paper, scratching of Cu/dielectric line structures by pad asperities is investigated. First, the scratching criteria and the scratch-regime maps, constructed previously for monolithic layers based on contact mechanics are extended for the patterned layers. Then sliding experiments have been conducted on patterned Cu/dielectric surface layers of various linewidths using solid polymeric pins loaded into the fully plastically deformed state, as well as commercial CMP pads. Specifically, the role of the width of Cu and dielectric lines in comparison with the contact diameter is examined. The theoretical models predict that the scratch criteria for patterns with wide lines are the same as those for monolithic layers, whereas patterns with extremely narrow lines behave as composite layers with effective mechanical properties. Experimental results validate the scratch criteria based on contact mechanics.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-02
Language
English
Article Type
Article
Keywords

CHEMICAL-MECHANICAL PLANARIZATION; DEFECT GENERATION; COPPER CMP; HARDNESS; MODEL; AGGLOMERATION; NANOSCALE; CHEMISTRY; MIXTURES; CONTACT

Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.28, no.1, pp.96 - 105

ISSN
0894-6507
DOI
10.1109/TSM.2014.2375672
URI
http://hdl.handle.net/10203/245043
Appears in Collection
ME-Journal Papers(저널논문)
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