(A) programmable and flexible 10Gb/s transceiver with a FPGA

Abstract

Digital design automation software tools have been very successful in achieving performance gains over the past 50 years as system IC density continues to increase. As the design of these mixed signal systems increases, the simulation time for verifying new algorithms becomes a significant part of overall system development time. However, it cannot be accurately verified using existing verification tools. In this thesis, we propose a programmable and flexible 10Gb/s transceiver that is a structure in which all the analog blocks that can be reused are implemented in the IC and the digital blocks that have always been a problem due to the difficulty of verification are implemented in the FPGA as a verification tool of mixed signal systems.