(An) area-efficient double-error correcting BCH decoder using lookup tables = 참조 표를 이용하여 두 개의 오류를 정정하는 공간 효율적인 BCH 복호기

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As the degree of integration of DRAM and NOR flash memory increases, the probability of occurrence of error also increases. Therefore, there is a demand for error correction hardware capable of correcting errors at high speed in smaller size. In order to satisfy the fast response time and complexity of the DRAM design in the conventional case, Hamming code is often used for correcting one error. But an error correcting code capable of correcting more errors is needed. In this paper, we propose a space-efficient decoder structure of Bose-Chaudhuri-Hocquenghen (BCH) code which corrects two errors, which is a method satisfying this requirement. The proposed decoder structure is a new approach to correct two bit errors using a lookup table (LUT). We established a new property to reduce the size of the reference table, mathematically identified, and the actual hardware design and compared the difference between the existing structure and the proposed method. The proposed scheme has the effect of reducing the complexity to approximately 50% while keeping the delay time equivalent compared with the conventional scheme.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[iii, 22 p. :]

Keywords

memory; double error correcting; BCH code; low complexity; lookup table; 메모리; 두 개의 오류를 정정하는 부호; BCH 부호; 하드웨어 최적화; 참조표

URI
http://hdl.handle.net/10203/243329
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675437&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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