As the degree of integration of DRAM and NOR flash memory increases, the probability of occurrence of error also increases. Therefore, there is a demand for error correction hardware capable of correcting errors at high speed in smaller size. In order to satisfy the fast response time and complexity of the DRAM design in the conventional case, Hamming code is often used for correcting one error. But an error correcting code capable of correcting more errors is needed. In this paper, we propose a space-efficient decoder structure of Bose-Chaudhuri-Hocquenghen (BCH) code which corrects two errors, which is a method satisfying this requirement. The proposed decoder structure is a new approach to correct two bit errors using a lookup table (LUT). We established a new property to reduce the size of the reference table, mathematically identified, and the actual hardware design and compared the difference between the existing structure and the proposed method. The proposed scheme has the effect of reducing the complexity to approximately 50% while keeping the delay time equivalent compared with the conventional scheme.