(A) 690GHz varactor frequency tripler with $2^{nd}$ harmonic consideration

Abstract

Frequency tripler design for terahertz region is presented in this thesis. For harmonic generation, n-varactor is implemented in 65nm CMOS process as nonlinear device. In addition, a newly proposed frequency tripler adopting this device is also presented in this thesis. A proposed circuit can increase the accuracy of the design and conversion efficiency compared to conversional works. Especially, by considering $2^{nd}$ harmonic voltage swing effect, efficient $3^{rd}$ harmonic generation can be achieved. The proposed frequency tripler is designed and implemented in TSMC 65 nm technology. The simulation results of the proposed freuquency tripler show 23.48 dB conversion loss and -12.26 dBm EIRP with 0dBm DC power consumption at input frequency of 230 GHz and output frequency of 690 GHz.