(A) Study of Intrinsic Field-Effect Mobility in Graphene Field-Effect Transistors for Characterization and Optimization of Transconductance그래핀 FET의 트랜스 컨덕턴스 특성 평가 및 최적화를 위한 진성 이동도에 대한 연구

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For accurate evaluation and optimization of transconductance of graphene field-effect transistors (GFETs), extraction of intrinsic mobility based on transconductance excluding an effect of parasitic re-sistance is essential. In this thesis, a technique for extraction of parasitic-resistance-independent intrinsic field-effect mobility is proposed through de-embedding parasitic resistance in a single GFET. First, the effect of voltage drop across the parasitic resistance in a GFET was embedded in current-voltage equation of the GFET. With the modified current-voltage equation, the relation between the measured transconductance and the intrinsic field-effect mobility of the GFET was determined. Accordingly, the equa-tion for intrinsic field-effect mobility was defined. Before the de-embedding of the total parasitic resistance of the GFET with the proposed technique, the effect of un-gated region for top-gate was investigated. The un-gated region for top-gate was a component of parasitic resistance in top-gate sweep but not in back-gate sweep. Therefore, the effect of access resistance was shown through comparison of back-gate sweep and top-gate sweep. The significant difference between the GFET with un-gated region and the GFET without un-gated region was observed. Through de-embedding the total parasitic resistance, the intrinsic field-effect mobility was calculated. It was observed that the calculated mobility based on the proposed method has larger value than the mobili-ty value extracted from the conventional method. To confirm the accuracy of the intrinsic field-effect mobility from proposed technique, the external resistance experiment was conducted. Through addition of the various external resistances, the parasitic resistance was modulated in the single GFET without changing the channel property of the GFET. As a result, it was confirmed that the intrinsic field-effect mobility extracted from proposed methods was independent of parasitic resistance. The independence means that the effect of parasitic resistance on transconductance was fully de-embedded by the proposed technique. The technique was also applied in top-gate GFET with underlap structure which has asymmetrical parasitic source/drain resistance. Addition of various external resistances was utilized to make larger asymmetry. As a result, it was confirmed that the proposed technique was acceptable in underlap structure.
Advisors
Choi, Yang-Kyuresearcher최양규researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[ii, 37 p. :]

Keywords

Graphene; Field-Effect Transistor; Transconductance; Parasitic Resistance; Intrinsic Field-Effect Mobility; External Resistance Experiment; Parasitic Resistance Modulation; 그래핀; 전계효과 트랜지스터; 트랜스 컨덕턴스; 기생저항; 진성 전계효과 이동도; 외부 저항 실험; 기생저항 변조

URI
http://hdl.handle.net/10203/243252
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675357&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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