A low-power high-speed transceiver IC design techniques for NRZ-PAM-4 signalingNRZ/PAM-4 시그널링을 위한 저전력 고속 트랜시버 IC 설계 기술

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Recently, mobile, video-streaming, and cloud services have triggered explosive growth in data traffic at data centers. There are also growing demands for eco-friendly data centers to reduce power consumption. These trends strongly drive the demand for high-speed-and-power-efficient data center networks. This work presents: (1) the industry’s first 103.125 Gb/s reverse gearbox IC satisfying the OIF MLG 2.0 standard. The proposed IC is fabricated in 40 nm CMOS. The IC includes ten parallel 10G transceivers, four parallel 25G transceivers, and enables the transmission of multiple asynchronous 10- and 40-GbE data streams across $4 \times 25G$ physical lanes. Each transceiver adopts an all-digital open-loop controlled PI-based D/PLL. The proposed D/PLL architecture enables power-and-area efficient implementation while achieving acceptable jitter filtering. (2) A low-power mixed-mode 56 Gb/s PAM-4 transceiver is presented. The proposed PAM-4 transceiver is fabricated in 28 nm CMOS. The PAM-4 receiver employs one-tap FFE and two-tap DFE for covering the OIF-CEI-56G MR standard. The proposed FFE eliminating the first-post cursor ISI leads to better power efficiency compare to a direct feedback DFE by relaxing timing limitations for the DFE critical path from 1 to 2 UI.
Advisors
Bae, Hyeon-Minresearcher배현민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[vi, 69 p. :]

Keywords

multi-link Gearbox; MLG 2.0; 100-GbE; 10-GbE; 40-GbE; CDR; low-power transceiver; parallel transceiver; PAM-4; feedforward equalizer; 멀티-링크 기어박스; 100 기가 비트 이더넷; 10 기가 비트 이더넷; 40 기가 비트 이더넷; 클럭 데이터 복원기; 저전력 송수신기; 병렬 송수신기; 피드포워드 등화기

URI
http://hdl.handle.net/10203/242018
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675816&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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