Vertical tunneling filed effect transistor based on p++ silicon and MoS2 heterostructure

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Publisher
제 5회 한국 그래핀 심포지엄
Issue Date
2018-03-29
Language
English
Citation

제 5회 한국 그래핀 심포지엄

URI
http://hdl.handle.net/10203/241490
Appears in Collection
EE-Conference Papers(학술회의논문)
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