Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I-V method

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The threshold voltage instabilities and huge hysteresis of MoS2 thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS2 TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS2 TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS2 TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.
Publisher
IOP PUBLISHING LTD
Issue Date
2018-04
Language
English
Article Type
Article
Keywords

THIN-FILM TRANSISTORS; FIELD-EFFECT TRANSISTORS; SINGLE-LAYER WS2; GATE DIELECTRICS; GRAPHENE; PERFORMANCE; INTERFACE; MOBILITY; BULK

Citation

NANOTECHNOLOGY, v.29, no.17

ISSN
0957-4484
DOI
10.1088/1361-6528/aa9cc6
URI
http://hdl.handle.net/10203/241086
Appears in Collection
EE-Journal Papers(저널논문)
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