A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

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In this paper, we propose a low-jitter low-power digital multiplying delay-locked loop (MDLL) with a self-calibrated double reference injection scheme. To reduce jitter, the noisy edge of the oscillator is replaced by both the rising and falling edges of the clean reference, which results in 6-dB reduction in phase noise compared with a conventional single-edge injection MDLL. Reference spur caused by a frequency error of the oscillator, duty-cycle error of the reference, and circuit imperfection, such as offset and mismatch, is removed by employing three background feedback loops with a shared analog pulsewidth comparator. Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of -51.4 dBc and an rms jitter of 699 fs(rms) while consuming 1.5 mW from 1-V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-11
Language
English
Article Type
Article
Keywords

PHASE-NOISE; CHARGE-PUMP; PLL; CMOS

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.11, pp.2934 - 2946

ISSN
0018-9200
DOI
10.1109/JSSC.2017.2734910
URI
http://hdl.handle.net/10203/227045
Appears in Collection
EE-Journal Papers(저널논문)
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