An Integrated Dual-Mode CMOS Power Amplifier With Linearizing Body Network

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A dual-mode radio frequency CMOS power amplifier (PA) for Internet of Things application is presented, which is integrated with the other circuits in a 55-nm bulk CMOS process. The low-power mode is achieved by reducing the number of turn-on power transistors, which are also used for linearization. The PA has a gain control scheme that functions by controlling the transconductance (gm) of the driver stage. A simple body network is introduced to common gate power transistors to improve the linearity of the PA. It is measured with 802.11n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 16 dBm with a supply current of 222 mA under an error-vector-magnitude of -27 dB, which is packaged in a QFN 5 x 5 mm.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-09
Language
English
Article Type
Article
Keywords

COMPREHENSIVE ANALYSIS; LDMOS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.9, pp.1037 - 1041

ISSN
1549-7747
DOI
10.1109/TCSII.2016.2624302
URI
http://hdl.handle.net/10203/226127
Appears in Collection
EE-Journal Papers(저널논문)
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