An Efficient Crosstalk-Included Eye-Diagram Estimation Method for High-Speed Interposer Channel on 2.5-D and 3-D IC

In this paper, we first propose an efficient crosstalk-included eye-diagram estimation method for high-speed interposer channel on 2.5-D and three-dimensional (3-D) IC. The proposed method includes crosstalk effects from adjacent channels, which can considerably degrade the transmitted signal on a victim channel. This method enables to estimate worst and statistical eye-diagrams in a short time with high accuracy. While 3-D EM simulation has been widely used for accurate estimation of the channel performance, it requires substantial amount of computational time and resources. Therefore, in order to reduce the eye-diagram estimation time, the coupled microstrip channels are modeled using resistance, inductance, conductance, and capacitance components, whose values are derived from the physical dimensions. The equivalent circuit model can also enhance physical insight of the coupled channels. The proposed method is verified by time-domain simulations and measurements at data rates of up to 4 Gb/s. According to the estimated crosstalk-included eye-diagrams, the proposed method reduces simulation time over 99% and shows a high accuracy of approximately 93%. The proposed method is applied to the high-bandwidth memory channels on silicon, organic, and glass interposer.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-06
Language
English
Keywords

SILICON INTERPOSER; LOW-COST; VIAS

Citation

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.59, no.3, pp.927 - 939

ISSN
0018-9375
DOI
10.1109/TEMC.2016.2630080
URI
http://hdl.handle.net/10203/223648
Appears in Collection
EE-Journal Papers(저널논문)
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