High-speed ADCs using time-domain signal processing = 시간영역 신호처리를 이용한 고속 아날로그 디지털 변환기 연구

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As networks have been developing in recent years, the data rate between computing devices (via wireline or wireless) has been increasing. For these communications, the demand for high-speed and moderate resolution analog-to-digital converter (ADC) has also been increasing. However, the modern CMOS process is not friendly to the analog and mixed signal circuits due to the drastic scale-down. Because of the low intrinsic gain of the modern CMOS process's transistor, it is hard to achieve a high-precision amplifier. On the other hand, the modern CMOS process has fast edge transitions due to low parasitic capacitance, leading to high-performance digital circuits. In order to cope with the barriers presented to analog circuits, the author claims that the time-domain signal processing is suitable analog design methodology for the modern CMOS process. The time-domain signal has digital-like waveform which takes advantage of the modern CMOS process. The author improves two types of ADCs using the time-domain signal processing: (1) an ADC using time-domain quantization and (2) an ADC using zero-crossing time information. By adopting time-domain signal processing, the ADCs can take advantage of the fast edge transition property of the modern technologies. At high speeds, the ADC using the time-domain quantization has two challenges: (1) nonlinearity and large power consumption of the voltage-to-time converter and (2) small time-resolution, $T_LSB$, required for proper linearity. First, since the input signal is in the voltage-domain, there should be a domain converter prior to the time-domain quantizer. However, in order to create a linear conversion transfer function, the voltage-to-time converter (V2T) should use a power hungry ramp generator in conventional single-slope (SS) ADCs. Another problem is that $T_LSB$ becomes too small to resolve it as the sampling rate increases. This is because the fullscale of the time-domain signal, $T_FS$, is limited by the sampling period. For example, a single-slope architecture is one of the time-domain ADCs which have a ramp-generator as the V2T and a counter as the TDC. Unfortunately, its operating speed is substantially low due to the thermometric counting method. In order to achieve a 250MS/s, 9-bit ADC, the required quantization clock should be 128GHz to achieve $T_LSB$ of 7.8125psec. In order to increase the speed without sacrificing the linearity and without high frequency clock, the author proposes a multiphase-counting single-slope ADC, which quantizes the input signal in a two-step subranging manner without high frequency quantization clocks or multiple ramps. To increase the operating speed, the proposed ADC employs a 16-way time-interleaving technique, which enlarges T_FS sixteen times. Its power consumption is minimized by sharing a multiphase clock generator and a counter with sub-channels. The author also proposes a method to remove offset errors between the counter sequence and multiphases as well as a method to correct false decision due to the metastability of latches. As a result, the prototype SS-ADC achieves 250MS/s, 9-bit with only 500MHz of the quantization clock. The individualized and simplified V2T reduces power consumption further while ensuring an enough linearity. A prototype 9-bit ADC implemented in 90nm CMOS achieves 245fJ/c.s. with a DNL/INL of 0.25/0.36LSB and SFDR of 55.3dB at 250MS/s while consuming 7.12mW. In order to achieve a much higher sampling rate (>1GS/s), the author improves the ADC using zero-crossing time by applying the time-domain signal processing. Traditionally, a zero-crossing based circuit (ZCBC) is a promising technique for low-power, low-speed pipeline ADCs. Unfortunately, operating ZCBC ADC at speed near 1GS/s is quite challenging due to the delay of the zero-crossing detector (ZCD), which introduces nonlinear gain and offset errors. To alleviate the issue of nonlinearity, the author proposes a ZCBC pipeline ADC that employs a passive resistor as a current source. As its characteristic is inherently linear, the resistor-based ZCBC eliminates the input dependency of the inter-stage gain and offset errors, allowing simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with a large offset that results from high-speed operation. A prototype ADC implemented in 65nm CMOS achieves an SNDR/SFDR of 47.26dB/62.64dB at 1GS/s while consuming 46.52mW from 1V supply. From the results, it can be seen that the time-domain signal processing is well-suited analog design methodology for the modern scaled CMOS technology. Note that the representative characteristic of the modern CMOS process is hard to make high DC gain opamp. The time-domain ADC eliminates the opamps and calculates the signal in the time-domain, leading to performance improvements. Therefore, the time-domain analog signal processing should be investigated further in order to exploit the modern CMOS technology, to reduce the power consumption, and to increase the speeds.
Advisors
Cho, SeongHwanresearcher조성환researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2016
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2016.2 ,[ix, 92 p. :]

Keywords

analog integrated circuit; mixed mode signal; analog to digital converter; ADC; single slope; two step; zero-crossing based circuit; ZCBC; pipelined ADC; high speed; 아날로그 IC; 데이터 컨버터; 아날로그 디지털 변환기; 고속; 파이프라인

URI
http://hdl.handle.net/10203/222371
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=648237&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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