High PSRR low dropout voltage regulator with an improved subtraction topology

Abstract

Recently, there are a demand for low dropout voltage regulator (LDO) with high power supply rejection (PSR) performance, using low power, wireless communication circuit for internet of things (IoT). This paper presents that an improved two stage low dropout regulator (LDO) is presented. In the proposed LDO, power supply rejection ratio (PSRR) is improved by using a subtraction topology containing a source follower connect-ed with a power transistor. This source follower buffer makes it possible to obtain high PSR and fixed current bias in the buffer. Simulation results show the PSR of 74 dB at 100 kHz. The presented LDO dissipates $33 \mu A$ under a 1.2 V supply in $0.18\mu m$ CMOS and occupies $0.058mm^{2}$. Proposed LDO have a stable current bias using a source-follower-buffer. Source-follower-buffer makes a special open loop gain that make the PSRR enhancement of the performance of circuits using proposed LDO. The proposed idea is very simple to apply any LDO using single power supply. The proposed subtraction con-cept for a improved PSRR can be adapted in cap-less LDO that can provide high performance PSRR to surpass gain of the amplifier and wide band PSRR also.