(A) low-power low-latency image segmentation method exploiting resistor grid

Abstract

Currently, computation demands in mobile devices grow rapidly with the advance of various vision applications. However, power system cannot follow up ever-increasing computation necessity. In this sense, processing visual data becomes crucial concern for the devices in resource poor environment. In addition, several mobile applications have low latency requirement to generate information from vision processing for adequate responses. Therefore, fast and energy efficient vision accelerator is strongly necessary. Among many vision problems, image segmentation is one of the basic processing techniques utilized for not only semantic observations but also more complex vision algorithms like object classification or tracking. In order to handle the problem, numerous algorithms and architectures have been suggested. Graph cuts algorithm is promising and widespread algorithm for image segmentation, image denoising, and stereo matching. It is based on the max flow/min cut theorem which states that the maximum flow in network is equal to the minimum cut solution. By exploiting the analogy from the graph cuts to electric current, approx-imate solutions of graph cut algorithm can be achieved in fast and energy efficient manner. In this work, we discuss some observations of graph cuts and resistor networks, then propose hard-ware efficient cut extraction schemes using simple voltage comparison. Resistor grid is generated by trans-forming segmentation problem into network graphs consisting of resistors and switches. Resistors role as edg-es connecting nodes (pixels), and switches give segmentation seeds of desired images. After the data trans-mission of the given image, resistor grid starts to flow currents over the resistors. When the currents becomes stable, the voltage distributions of all nodes show implication to the graph cuts solution. Approximation based on some observations allows us to use voltage threshold to divide images into the background and the foreground. To implement the algorithm, 64 by 64 prototype circuit using 65nm CMOS technology is designed. Most of the circuits are composed of resistors to construct the programmable grid for the image segmentation problem. And, cut extraction block using proposed scheme is attached to each resistor rows to efficiently exe-cute segmentation process. Using public GrabCut benchmark, verifications of circuit evaluations are performed. As a result, we can ascertain low-latency and energy efficient image segmentations with acceptable accuracy. Speed effi-ciency is 4.57 times faster than other image segmentation works. Moreover, energy efficiency is 9.11 times better when compared to other image/video segmentation papers.