UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs

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dc.contributor.authorZiabari, Amir Kavyanko
dc.contributor.authorSun, Yifanko
dc.contributor.authorMa, Yenaiko
dc.contributor.authorSchaa, Danako
dc.contributor.authorAbellan, Jose L.ko
dc.contributor.authorUbal, Rafaelko
dc.contributor.authorKim, Johnko
dc.contributor.authorJoshi, Ajayko
dc.contributor.authorKaeli, Davidko
dc.date.accessioned2017-03-28T06:57:10Z-
dc.date.available2017-03-28T06:57:10Z-
dc.date.created2017-02-20-
dc.date.created2017-02-20-
dc.date.issued2016-12-
dc.identifier.citationACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.13, no.4-
dc.identifier.issn1544-3566-
dc.identifier.urihttp://hdl.handle.net/10203/220982-
dc.description.abstractIn this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. UsingUMHwith NMOESI improves performance of a CPU-multiGPU system by at least 1.92x in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13x faster.-
dc.languageEnglish-
dc.publisherASSOC COMPUTING MACHINERY-
dc.subjectDESIGN-
dc.subjectARCHITECTURE-
dc.subjectMANAGEMENT-
dc.titleUMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs-
dc.typeArticle-
dc.identifier.wosid000392416400004-
dc.identifier.scopusid2-s2.0-85007002393-
dc.type.rimsART-
dc.citation.volume13-
dc.citation.issue4-
dc.citation.publicationnameACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION-
dc.identifier.doi10.1145/2996190-
dc.contributor.localauthorKim, John-
dc.contributor.nonIdAuthorZiabari, Amir Kavyan-
dc.contributor.nonIdAuthorSun, Yifan-
dc.contributor.nonIdAuthorMa, Yenai-
dc.contributor.nonIdAuthorSchaa, Dana-
dc.contributor.nonIdAuthorAbellan, Jose L.-
dc.contributor.nonIdAuthorUbal, Rafael-
dc.contributor.nonIdAuthorJoshi, Ajay-
dc.contributor.nonIdAuthorKaeli, David-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorUnified memory architecture-
dc.subject.keywordAuthormemory hierarchy-
dc.subject.keywordAuthorgraphics processing units-
dc.subject.keywordAuthorhigh performance computing-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusMANAGEMENT-
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