More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs

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Low-power is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant power saving over 2-D ICs. However, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper, we extend our target to three-tier (3-tier) 3-D ICs. This paper first shows that the one additional tier available in 3-tier 3-D ICs does offer more power saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second, we find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined. This paper shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3-D ICs provide -14.8% more power reduction over 2-tier 3-D ICs, and -36.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide -27.2% more power reduction over 2-D ICs.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.35, no.12, pp.2056 - 2067

ISSN
0278-0070
DOI
10.1109/TCAD.2016.2550583
URI
http://hdl.handle.net/10203/219614
Appears in Collection
RIMS Journal Papers
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