A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

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A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit, The cell delay of the ring oscillator is smaller than a fundamental inverter delay, Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1997-02
Language
English
Article Type
Article
Keywords

DIGITAL CLOCK; CMOS

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.2, pp.289 - 291

ISSN
0018-9200
URI
http://hdl.handle.net/10203/21919
Appears in Collection
RIMS Journal PapersEE-Journal Papers(저널논문)
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