DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing

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It is widely known that relatively long DRAM latency forms a bottleneck in computing systems. However, DRAM vendors are strongly reluctant to decrease DRAM latency due to the additional manufacturing cost. Therefore, we set our goal to reduce DRAM latency without any modification in the existing DRAM structure. To accomplish our goal, we focus on an intrinsic phenomenon in DRAM: electric charge variation in DRAM cell capacitors. Then, we draw two key insights: i) DRAM row-access latency of a row is a function of the elapsed time from when the row was last refreshed, and ii) DRAM row-access latency of a row is also a function of the remaining time until the row is next refreshed. Based on these two insights, we propose two mechanisms to reduce DRAM latency: NUAT-1 and NUAT-2. NUAT-1 exploits the first key insight and NUAT-2 exploits the second key insight. For evaluation, circuit-and system-level simulations are performed, which show the performance improvement for various environments.
Publisher
IEEE COMPUTER SOC
Issue Date
2016-10
Language
English
Article Type
Article
Keywords

MEMORY; PERFORMANCE; SYSTEMS; ARCHITECTURE; FAIRNESS

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3027 - 3040

ISSN
0018-9340
DOI
10.1109/TC.2015.2512863
URI
http://hdl.handle.net/10203/213861
Appears in Collection
EE-Journal Papers(저널논문)
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