A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

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This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-02
Language
English
Article Type
Article
Keywords

SOI CMOS TECHNOLOGY; DECISION-FEEDBACK EQUALIZER; NM CMOS; 0.13-MU-M CMOS; TRANSCEIVER; RECEIVER; OSCILLATORS; CLOCK

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.2, pp.789 - 793

ISSN
1063-8210
DOI
10.1109/TVLSI.2015.2418579
URI
http://hdl.handle.net/10203/207637
Appears in Collection
EE-Journal Papers(저널논문)
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